1. Field of the Invention
The present invention generally relates to integrated circuits and more particularly to controlling the threshold voltage of semiconductor devices using halo structures.
2. Description of the Related Art
Conventional integrated circuit device structures are continuously being reduced in size to increase processing speed and decrease manufacturing cost. Conventional methods of reducing the size of such devices shrink all the dimensions of the device proportionally.
However, as the channel length in the metal oxide semiconductor field effect transistors (MOSFETs) is reduced to increase speed, axe2x80x9cshort-channelxe2x80x9d effect often occurs which severely degrades the device characteristics. More specifically, the short channel effect is an undesirable decrease in the threshold voltage of the gate as the channel length is reduced. Additionally, the scalability of the planar MOSFET in this environment is severely limited by reliability imposed constraints on minimum gate insulator thickness and poor physical attributes such as excessive buried strap outdiffusion, for trench storage DRAMS active area (AA) and gate conductor (GC) critical dimension control, gate conductor-deep trench (GC-DT) overlay tolerance, shallow trench isolation (STI) recess and geometry control.
One specific manifestation of the scalability difficulties of planar dynamic random access memory (DRAM) MOSFETs is degradation of the retention time tail, due to increased junction leakage resulting from the very high channel doping concentrations which are required to suppress the short-channel effects.
Therefore, there is a conventional need for a method and structure which overcomes these scalability problems to produce more consistent threshold voltages.
It is, therefore, an object of the present invention to provide a structure and method for manufacturing an integrated circuit device including forming a transistor, adjacent a storage device, to include a storage node diffuision region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the transistor, patterning a mask over the transistor to expose the bitline contact diffusion region, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the transistor adjacent the bitline contact diffusion region, removing the mask, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the structure to drive the halo implant ahead of the impurity.
The implanting of the impurity includes patterning a first mask over the transistor to expose the storage node diffusion region, implanting the impurity into the storage node diffusion region using a first doping concentration, removing the first mask, patterning a second mask over the transistor to expose the bitline contact diffusion region, implanting the impurity into the bitline contact diffusion region using a second doping concentration, wherein the second doping concentration is higher than the first doping concentration and removing the second mask. The second doping concentration is approximately 10 times the first doping concentration.
The implanting may be an angled ion implantation and a geometry of the transistor, the insulator layer and the bitline contact diffusion region allows ions applied at an angle up to approximately 30xc2x0 to the normal of a surface of the bitline contact diffusion region to reach the bitline diffusion region.
The method may also include forming support devices, wherein the implanting of the impurity includes implanting the impurity into source and drain regions of the support devices, and wherein the implanting of the halo implant includes implanting selected ones of the support devices with the halo implant. The invention also forms a patterned insulator layer over the transistor and the support devices (the patterned insulator layer including bitline contact openings, support source openings and support drain openings) and simultaneously deposits a conductor in the bitline contact openings, the support source openings and the support drain openings, wherein the conductor may be tungsten.
The invention forms a P-type halo which surrounds the N+ bitline diffusion region. Since the threshold voltage and short-channel effects of the array MOSFET are dominated by the halo, the normally implanted channel doping concentration may be greatly reduced, which allows the invention to achieve improved array threshold voltage (VT) control without increased node diffusion leakage. Furthermore, the invention allows the use of tungsten studs, which are normally only used in the supports, to be used in the array, as well.